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AI chip supply chain bottlenecks

Discussed in 1 analyzed podcast episode across 1 show

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Episodes

Cheeky Pint · Feb 26, 2026

Reiner Pope of MatX on accelerating AI with transformer-optimized chips

Transformer-optimized chip architecture HBM vs SRAM memory trade-offs in AI inference Systolic array design and optimization Low-precision arithmetic (4-bit, mixed-precision)TSMC manufacturing and tape-out process